During semiconductor fabrication a conventional process starts with a wafer substrate 10, as depicted in FIG. 1, that has patterned thin oxide layers 12 separating isolation regions of thick (or field) oxide 11. In the process depicted in FIG. 1, during exposure and patterning of photoresist 15 via reticle 16, light can reflect off of the uneven topology of silicide 14 and cause what is know as reflective notching. The reflective notching in the photoresist pattern is then transferred into the underlying conductive layer following a subsequent etch.
As seen from the top view of FIG. 2, a conductive strip 21 shows the results of reflective notching during the exposure of the photoresist that has caused some of the conductive strip to be removed during the etching of the strip. In this case the conductive strip 21 has been patterned over active area 22 to serve as a control gate to an MOS device. It becomes obvious that this reflective notch is undesirable as it would reduce the reliability of the MOS device.
The present invention addresses the reflective notching problem by forming a planarized conductor on a wafer's surface that has a uneven topology that results from the formation of spaced apart, patterned oxide isolation regions including oxide regions formed by LOCOS trench isolation and other advanced isolation technologies.